Research 012026
Read-Trace Consistency in Accelerator Simulation
Overview
Trace-based memory studies rely on the DRAM requests generated by an accelerator simulator. If a served read has no supporting transfer, the replay omits part of the memory traffic. We checked that correspondence in SCALE-Sim, then compared dataflow rankings across two measurement windows using configurations that passed the study’s admission checks.
01 contribution
I led a three-student team in the FDUROP Xiyuan Program, advised by Prof. Keren Zhu (CODA Lab). We developed a transfer-level consistency check for SCALE-Sim and evaluated 17 layer shapes from MobileNet V1 and DS-CNN-S on an 8×8 array, using output-, weight-, and input-stationary dataflows.
The question
Can every served read be traced to data that has already arrived?
A consistency check at the boundary between memory transfers and compute.
02 method
The observer follows prefetch, refill, hit queries, and read service, preserving their arguments, return values, and simulated timing. For each requested address, it checks that a generated transfer exists, that the earliest recorded completion is no later than the read’s return, and that the return respects the configured hit latency.
Controlled probes identified two mechanisms behind false hits. Null slots occupy positions in the prefetch schedule, reducing the addresses covered by an initial transfer. The hit logic rounds its budget up to whole groups of non-null occurrences, which can expand the set of reported hits. All 27 probes agreed with the transfer-based references and the predicted hit budget.
A transfer exists for the requested address.
tcomplete ≤ treturn
tarrival + Lhit ≤ treturn
Address-level observer
Keep the earliest transfer completion time for each address.
Test address coverage and timing; record the first violating service.
03 findings
All 612 runs completed normally. The read-causality check found violations in 333 of the 459 buffer-constrained configurations; all 153 large-buffer controls passed. These checks expose inconsistencies between the simulator’s read path and the transfers or service times recorded for it.
Buffer-constrained grid
333 / 459configurations failed the read check.
The operand-fit boundary
To examine the operand-fit boundary, we ran 150 configurations around the minimum capacity needed to hold each layer’s unique inputs and weights. Of the 102 configurations at or above that boundary, nine failed the check; all were weight-stationary. Their operands fit in the active buffer halves, yet the initial transfer missed addresses that the hit logic reported as resident.
In MN conv0 at 216 Ki words per operand buffer, the WS hit logic reported 110,592 input addresses as resident. The initial transfer covered 102,921 distinct addresses, leaving 7,671 false-hit addresses. Its 110,592-slot schedule prefix was shorter than the 131,052 slots needed to cover all required input addresses.
From trace consistency to design choice
We compared 51 configurations that passed the study’s admission checks. Switching between the compute field and the cold interval changed the set of fastest dataflows for 13 of the 17 layer shapes, with ties retained. In MN conv0, the same WS and OS runs reverse order between the two windows. A cycle count’s measurement window can therefore change the dataflow a designer would choose.
8×8 array · 512 Ki words per operand · 4 words/cycle
| Window | WS | OS |
|---|---|---|
| Compute field | 16,471lower | 20,991 |
| Cold interval | 82,006 | 56,830lower |
WS: weight-stationary. OS: output-stationary.
Original comparison · slide 704 outcome
I presented the study at ICICM 2026 in Xi’an on 17 October 2026. My oral presentation received the Best Presentation Award (session).
11th International Conference on Integrated Circuits and Microsystems (ICICM 2026)
Xi’an, China
Best Presentation Award (session)