Research 02Apr 2026 – present

Observing the GPU memory system.

GPU Memory-System Co-simulation

GPU memory-system simulation61,275accepted L2 accesses
matched by status.

Context: Undergraduate research · Fudan University
Contribution: L2 observer design & implementation
Focus: GPU · GPGPU-Sim · Memory Systems

Overview

Memory-system comparisons need events with precise timing and accounting semantics. Within a Fudan University project comparing a C++ GPU model with RTL, I built an optional L2 cache observer for GPGPU-Sim. It exposes accepted accesses through a small callback interface and makes each event traceable to the simulator’s native statistics.

01 contribution

An optional interface for cache events

I designed and implemented an optional callback interface for accepted L2 accesses in GPGPU-Sim. A consumer can register one observer per simulator instance and collect cache activity without putting tool-specific counters or dependencies into the simulator. I also added registration checks, directed cache tests, and usage documentation so that integrations have a defined event contract.

l2-cache-observer.h

void notify(
    const l2_cache_access_event
        &event
) const noexcept {
    callback_(context_, event);
}

Dispatch is synchronous. The caller owns the callback context and registers it for one simulator instance.

Read the source · BSD-3-Clause ↗

02 method

One accepted access, one event

With a callback registered, the observer reports an accepted call to the L2 data_cache::access() path after native statistics have been updated. An event carries the original access address, request metadata, access type, and statistics status. Separate GPU-cycle and cache-call timestamps preserve the two timing contexts. The status follows the same select_stats_status() result used by the simulator’s own accounting.

gpu-cache.ccdata_cache::access

Read the event at the point where the simulator accounts for the access.

Entrydata_cache::access

Native accountingUpdate cache statistics

Accepted L2 accessl2_cache_access_event

Observer dispatchl2_cache_events.notify(event)

With an observer registered, accepted L2 accesses produce events after native accounting. Read the interface documentation ↗

03 validation

Unchanged results in a three-way replay

I replayed the Rodinia backprop 4096 SASS traces in three configurations: the unmodified simulator, the candidate with no observer registered, and the candidate with an observer attached. All three completed both kernels with identical cycle and instruction totals and matching normalized output. The observer preserved the simulator’s reported behavior in this replay while exposing its accepted L2 accesses.

Directed production-cache tests also cover pending hits, sector misses, rejection and retry, address mutation, write allocation, non-global access types, and registration errors. Ten native-behavior summaries matched unmodified dev and remained unchanged with an observer attached and after unregistration.

Rodinia backprop 4096 · both kernels
Configuration	Simulated cycles	Simulated instructions
BaselineUnmodified dev	14,731	10,473,824
CandidateObserver unregistered	14,731	10,473,824
CandidateObserver registered	14,731	10,473,824

All 7,000 normalized output lines matched across the three runs. The registered observer recorded 61,275 events, matching the native accepted-access count in every status bucket.

The comparison excludes build banners, wall-clock and rate lines, and the observer summary. Trace-replay validation in PR #151 ↗

04 outcome

A public simulator contribution

I submitted the observer, its documentation, and opt-in tests as pull request #151 to Accel-Sim’s GPGPU-Sim repository. The pull request is open for review.

Open-source contributionL2 cache observerAccel-Sim / GPGPU-SimOpen pull request · #151