Research 03Oct–Nov 2026

From model predictions to routed arrays.

Model2GDS — Reproducible Systolic-Array Design

Actual Model2GDS 4 by 4 routed array, with original routing colors and physical scale. — 4×4 routed array · 20 ns study

Context: Individual project · ISSCC 2027 Code-a-Chip
Contribution: Individual project author
Focus: Model-to-RTL · Systolic Arrays · EDA

Overview

Model2GDS is my individual ISSCC 2027 Code-a-Chip project, now merged into the official IEEE SSCS repository. I built an executable path from independent numerical and token-cycle models to recorded RTL behavior across three systolic-array sizes. The notebook also connects routed 2×2 and 4×4 implementations to their physical-design records and area estimates.

01 contribution

An executable path from model to RTL

Model2GDS is my individual ISSCC 2027 Code-a-Chip project. I developed the independent numerical and token-cycle models, parameterized SystemVerilog RTL, and verification workflow, then connected them in an executable notebook. Readers can replay the comparisons from preserved inputs and RTL observations, through parsers and structured results, to the figures shown here. The physical implementation uses an existing open-source RTL-to-GDS toolchain.

A connected workflow

01 Token-level model
02 Parameterized RTL
03 Verification & implementation

2 by 2 output-stationary array with K equals 2: tokens propagate through registered neighbors and finish in five rising edges including clear. — Figure 01 · Token propagationA 2×2 example with K=2 completes in five counted rising edges, including clear. The diagram follows aligned tokens through registered neighbor connections.View full resolution (new tab)

Registered neighbor links — original figure, left panel — Figure 01 · Token propagationA 2×2 example with K=2 completes in five counted rising edges, including clear. The diagram follows aligned tokens through registered neighbor connections.View full resolution (new tab)

02 validation

Exact agreement across three array sizes

The numerical model checks matrix-multiplication results; the token-cycle model predicts completion in counted rising clock edges. Across the 2×2, 4×4, and 8×8 arrays, both models matched the recorded RTL in all 441 test runs. The maximum absolute cycle difference was zero. These checks make the array’s arithmetic and completion timing independently reproducible.

441/441

numerical and cycle checks matched

Maximum cycle difference: 0

2×2 · 4×4 · 8×8 arrays

Log-log plot of token-model versus RTL-observed counted rising edges. All 441 executions lie on the equality line; maximum absolute difference is zero. — Figure 02 · Model / RTL agreementModel predictions and RTL observations lie on the equality line, with 147 executions for each array size.View full resolution (new tab)

Explore the verification case plan

Each array uses 13 directed cases, 128 deterministic random cases, and 6 frozen-workload sanity checks.

Each of the 2 by 2, 4 by 4 and 8 by 8 arrays runs 13 directed, 128 deterministic random and 6 frozen-workload sanity checks, totaling 147 per array. — Figure 03 · Verification coverageThe same deterministic case plan is used across the three array sizes.View full resolution (new tab)

03 physical

Routed 2×2 and 4×4 arrays

I implemented the 2×2 and 4×4 arrays in SKY130 with a 20 ns clock target using an open-source RTL-to-GDS flow. The routing views and area figures below come from that implementation study. Its recipe, metric extraction, and saved physical-design records are included in the notebook’s supplement, so readers can trace each reported value to its source.

20 ns

Implementation constraint

2×2 and 4×4 arrays · SKY130

Real 2 by 2 array routing overview with original layer colors, a 50 micrometer scale bar, and a dashed center-detail marker. — Figure 04 · 2×2 routing2×2 top-cell routing, with a 50 µm scale bar. The dashed box marks the center-detail view included in the original figure.View full resolution (new tab)

Real 4 by 4 array routing overview with original layer colors, a 100 micrometer scale bar, and a dashed center-detail marker. — Figure 05 · 4×4 routing4×4 top-cell routing, with a 100 µm scale bar. The dashed box marks the center-detail view included in the original figure.View full resolution (new tab)

Area from the 20 ns implementation study
Array	Cell area µm²	Floorplan core area µm²
2×2	39,103.8	130,964
4×4	162,386.0	531,820

Source: the 20 ns implementation record ↗. Each routing view retains its own physical scale.

04 outcome

Merged into IEEE SSCS Code-a-Chip

IEEE SSCS merged Model2GDS into its official Code-a-Chip repository through PR #205. The notebook, RTL, verification cases, preserved results, and reproduction instructions are available together in the ISSCC 2027 submission directory.

ISSCC 2027 · IEEE SSCSModel2GDSNotebook, RTL, tests & implementation recordsContribution merged · #205

From model predictions to routed arrays.

An executable path from model to RTL

Exact agreement across three array sizes

Routed 2×2 and 4×4 arrays

Merged into IEEE SSCS Code-a-Chip

Further reading